Meeting date: 16 may 2006
Members (asterisk for those attending):
Arpad Muranyi, Intel Corp.
*Bob Ross, Teraspeed Consulting Group
*Todd Westerhoff, Cisco Systems
*Mike LaBonte, Cisco Systems
Paul Fernando, NCSU
Barry Katz, SiSoft
Walter Katz, SiSoft
Ken Willis, Cadence Design Systems
*Ian Dodd, Mentor Graphics
Lance Wang, Cadence Design Systems
*Richard Ward, Texas Instruments
*Doug White, Cisco Systems
Sanjeev Gupta, Agilent
*Joe Abler, IBM
*John Shields, Mentor Graphics

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Review of ARs:

- no ARs

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Encryption:
- We want to keep people from viewing data, but simulator can use it.
- Latest IEEE Verilog standard 1364.2005 recently ratified
  - Has an encryption mechanism.
- VHDL language under revision now
  - Proposing same mechanism as Verilog.
  - Developed at Accellera.
  - Will be passed on to IEEE 6 mos. after Accellera ratification (by DAC).
- Encryption used by both
  - Pragmas delimit encrypted section.
  - Symmetric cypher keeps the key.
  - Digital envelope concept:
    - Take advantage of fast symmetric key encryption.
    - But hard to keep keys secret
      - Wrap secret key in a public-key encryption.
  - Data authentication signatures.
  - Markup language fits both Verilog and VHDL.
- Trusted users concept:
  - End user is not trusted.
  - Tool developers are trusted.
- Accellera proposal:
  - Organization shares secret key with vendor.
  - User receives encrypted source, tool picks up key from owner.
  - Model vendors qualify the EDA tools that can have the key.
  - Standard doesn't describe specifically how to do key management, but:
    - Hypothetical "lousy" tool:
      - Get secret key from "ACME".
      - Embed key in executable.
    - Hypothetical "good" tool;
      - Use secure key chain.
      - Create an encrypted database with the key embedded.
      - Secret key is used to decrypt database and get the data decryption key.
  - Have to create a different model for each vendor.
- For the short term transition period:
  - Use vendor proprietary methods.
  - Some vendors will move to standardized method.
- Will there be 3rd parties providing the mechanism?
  - AMS community knows compliance takes a long time.
  - FPGA vendors are pressing for encryption on the digital side.
  - We need to do some promotion to get EDA tools implementing.
- Licensing mechanism:
  - Can license per user.
  - Fairly weak, could be broken.
- Viewport directive:
  - Allows read/write access to specific parts of a model.
  - Makes model more usable.
  - VHDL shuts down certain APIs that could compromise protected models.
- Where are the documents?
  - Verilog standard completed, PDF at IEEE
  - VHDL is at Accellera, not sure if our group can get it:
    - May be easier for outsiders to understand.
    - Some of us are Accellera members.
- Maybe John Shields could present at the upcoming DAC IBIS Summit.

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Next meeting: Tuesday 23 may 2006 12:00pm PT